High-speed serial data links are used in many applications. An example of such a data link is described in the “Serial ATA Revision 2.5 Specification,” 27 Oct. 2005, by the Serial ATA International Organization, the entirety of which is hereby incorporated by reference herein for all purposes as if fully set forth herein (ATA is an acronym for Advanced Technology Attachment, a disk drive interface standard based on the IBM Personal Computer Industry Standard Architecture (ISA) 16-bit bus but also used on other personal computers).
In some applications of high-speed serial data links, such as a serial ATA (SATA) full duplex high-speed serial data link, the receiver at each end of the data link recovers the receive clock from the received data signal.
FIG. 1 illustrates an example of a system 100 employing a high-speed serial data link where the receivers at each end of the data link recover the receive clock from the received data signal. System 100 includes a first (host) transceiver 110, a second (device) transceiver 150, a first local clock 120, and a second local clock 170. First transceiver 110 includes a transmitter 112 and a receiver 115, while second transceiver 150 includes a transmitter 152 and a receiver 155.
First local clock 120 supplies a transmit clock to transmitter 112 at the first (host) end, and second local clock 170 supplies a transmit clock to transmitter 152 at the second (device) end of the link.
In many applications of a high-speed serial data link, such as a SATA data link, a precision clock signal is required at each end of the data link. In systems with a high-speed serial data link requiring a precision clock signal at each end, a crystal oscillator can be used at each end of the data link to generate the required precision local clock signal.
However, a crystal oscillator adds cost to the transceiver at each end, and it would be desirable to replace the crystal oscillator where possible with a cheaper ceramic resonator.
Accordingly, if the transmitter at one end (e.g., the device end) of the data link could use the recovered clock that was generated at the far end (e.g., host end) of the data link, then the device could generate its transmit clock using the much cheaper ceramic resonator, instead of a crystal source.
FIG. 2 illustrates an example of a system 200 employing a high-speed serial data link that utilizes a recovered receive clock from a received data signal to produce the transmit clock at one end of the data link. System 200 includes a first (host) transceiver 210, a second (device) transceiver 250, a first local clock 220, and a second local clock 270. First transceiver 210 includes a transmitter 212 and a receiver 215, while second transceiver 250 includes a transmitter 252 and a receiver 255.
First local clock 220 supplies a transmit clock to transmitter 212 at the far end (host end of the data link. Meanwhile, receiver 255 recovers a receive clock signal from the received data signal, and provides the recovered receive clock to transmitter 252 as a transmit clock 270.
Receiver 255 can employ an analog tracking receiver to recover the receive clock to be employed in generating the transmit clock.
However, such an approach has some disadvantages. Specifically, in many applications such as a SATA high-speed serial data link, the transmit clock has more stringent requirements than are required for the recovered receive clock. More specifically, there are requirements that limit the amount of jitter that is permitted on the transmit clock. In that case, the above-described approach suffers from the fact that the system level transmit clock jitter requirements are passed down to the clock data recovery (CDR) circuit in the receiver. This in turn leads to a more complex and power-hungry design than would otherwise be necessary. For example, the oscillator in the receiver CDR typically must use more power to get the random phase noise down to a level that is acceptable for the transmit clock. Furthermore, digital CDR circuits (which generally have lower power requirements and occupy less area than analog circuits) generally produce a clock signal whose jitter is too great for applications such as the SATA specification described above. A hybrid analog/digital CDR may be employed, but again this comes at the expense of increased power consumption and increased area.
Therefore, it would be desirable to provide a high-speed serial data link which operates with a single precision clock source. It would also be desirable to provide a clock generating circuit for a high-speed serial data link that can operate without a crystal source.
In accordance with an example embodiment, a clock generator for a transmitter in a transceiver is adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit adapted to recover a receive clock and to output a reference clock signal derived from the recovered receive clock. The clock generator comprises: a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock is adapted to output a local clock signal. The frequency difference detector is adapted to receive the local clock signal and the reference clock signal output from the clock data recovery circuit, and to output a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer is adapted to receive the local clock signal and the fractional frequency difference signal and to output a transmit clock signal having a same frequency as the recovered receive clock signal.
In accordance with another example embodiment, a transceiver is adapted to communicate data over a serial data link. The transceiver comprises a transmitter having a transmitter clock input; a receiver including a clock data recovery circuit having a reference clock output; and a clock generator. The clock generator comprises: a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock has a local clock output. The frequency difference detector includes: a first clock input connected to the reference clock output of the clock data recovery circuit, a second clock input connected to the local clock output, and a frequency difference output. The fractional-N frequency synthesizer includes a reference clock input connected to the local clock output, a frequency offset input connected to the frequency difference output of the frequency difference detector, and a transmit clock output connected to the transmitter clock input.
In accordance with yet another example embodiment, a method is provided for generating a transmit clock signal for a transceiver communicating over a high-speed data link. The method comprises: comparing a local clock signal with a reference clock signal derived from a recovered receive clock signal, and determining a frequency difference between the local clock signal and the reference clock signal; and using the local clock signal and the frequency difference to synthesize the transmit clock signal in a fractional-N frequency synthesizer, where the fractional-N synthesizer determines a frequency of the transmit clock signal as an integer multiple of a frequency of the local clock signal, plus a fractional multiple of the frequency of the local clock signal, where the fractional multiple is determined by the frequency difference between the local clock signal and the reference clock signal.